The present invention relates to a method and apparatus of pattern inspection and a semiconductor inspection system, which inspect a pattern formed on a wafer with use of a photographed image of a semiconductor device and design data on the semiconductor device.
Since recent semiconductor devices are miniaturized, increased in the number of layers, and made complicated in logic; it is highly difficult to manufacture such semiconductor devices. As a result, a frequency of failure caused in a manufacturing process tends to increase and it become important to accurately detect its failure position through inspection. Failures caused by the manufacturing process include pattern deformation caused by improper exposure conditions and continuity failure caused by a positional offset between layers. The locations of such failures are detected by collating design data, such as CAD data (Computer Aided Design data) about a semiconductor device with a pattern formed on a wafer. The semiconductor design data, such as CAD data is used to determine a layout of a pattern to be formed on the semiconductor device. The design data has various formats including GDS and OASIS, which employ, in common, a so-called vector data format wherein a group of feature points of a pattern are described. This is because the high integration of a semiconductor involves an enormous amount of pattern information. In this case, a semiconductor manufacturing apparatus or a semiconductor inspection apparatus using such design data recognizes a pattern shape by drawing a straight line between feature points.
In recent circuit design, an attempt is made to simulate how designed data is distorted by a semiconductor manufacturing process and to control a wiring density and so on on the basis of the simulated result in order to design a failure-proof circuit. For the purpose of increasing the accuracy of the above simulator, a pattern actually formed on a wafer is compared with a distorted pattern based on the design data issued from the simulator, and a difference in shape between the patterns is fed back to the simulator.
One of devices for inspecting a pattern with use of design data and an image of a semiconductor device is proposed in JP-A-2000-293690. In the publication, design data of layers included in a photographed image is used, and matching operation between the design data and a pattern extracted from the photographed image is carried out, to thereby detect a measurement position in the pattern and to measure the pattern.
However, when patterns of a plurality of layers are included in the photographed image, pattern inspection cannot be realized independently for each layer. In other words, the prior art device does not detect layer information about plural layer patterns included in the photographed image, and performs pattern matching operation with the design-data-based pattern of a single layer corresponding to a superposition of the patterns of the plural layers. For this reason, when patterns corresponding to a plurality of layers are included in the photographed image, the prior art device has a problem that the device fails to perform the pattern matching operation under the influence of the patterns of the layers other than a target layer to be inspected and thus cannot accurately measure the pattern.
Also disclosed in JP-A-2000-299361 is a method for performing pattern matching operation between an image of a semiconductor including plural layer patterns and design data of plural layers which added and superimposed offset and for measuring an actual offset. As in the above prior art device, even the disclosed method also has the following problem. Since the detection of layer information is not carried out with respect to a pattern extracted from the photographed image, it is required to increase the measurement accuracy by providing an increased number of variations in the offset upon overlap of the design data. However, this disadvantageously involves an increased processing time, thus reducing an inspection efficiency.